The present invention relates generally to scan testing and memory built-in self test (BIST) of integrated circuits and, more particularly, to a system and method for performing a scan test and a memory BIST test on integrated circuits using a scan bypass and a BIST bypass.
In recent years there have been tremendous advancements in the fields of semiconductor devices and electronic circuit integration. Currently, a single system-on-chip (SoC) with multiple package types or options is available. In small package embodiments, certain functional intellectual property (IP) blocks may be masked out depending on the selected package type. The masked out IP blocks may include combinational logic blocks and memory blocks.
FIG. 1 is a schematic diagram illustrating scan testing using scan chain design and memory testing using BIST controllers in system that includes both scan and BIST test systems. That is, scan testing is performed on an integrated circuit (IC) 10 having a plurality of scan chains 12 using an automatic test equipment 14 (ATE), which employs a deterministic automatic test pattern generation (ATPG). The IC 10 also may have a plurality of BIST controllers 15 for testing memory modules (not shown) using the ATE 14. The ATE 14 inputs compressed scan test patterns to the IC 10. The IC 10 includes a decompressor 16 that receives and decompresses the scan test patterns and provides the decompressed test patterns to the scan chains 0-N 12 such that all of the flip-flops of the IC 10, including those of unused functional circuit blocks, are tested for faults. The scan test response from the scan chains 12 are output to a compressor 18, which compresses the scan test response and then provides the compressed scan test response to the ATE 14 where it is compared with expected scan responses to determine whether the IC 10 has any faults. Similarly, memory test patterns are generated and provided to the BIST controllers 0-M 15 for testing memory blocks of the IC 10.
If any faults exist and are detected in the masked-out blocks, the IC 10 will be discarded. However, the IC 10 may still be operable for other package types in which the masked-out blocks are not necessary for functional operation. Thus, the full scan and full memory BIST tests may result in unintentional yield loss. It would be advantageous to be able to prevent unintentional yield loss due to faults only in the masked-out blocks.